The current application claims priority from Korean Patent Application Number 2001-0008798, entitled DEVICE FOR LINEARIZING POWER AMPLIFIER WITH PREDISTORTION IN IF BAND, which was filed on Feb. 21, 2001, all naming the same inventors and the same assignees as this application, which is incorporated by reference herein.
1. Field of the Invention
The present invention relates to a power amplifier and, more particularly, to a circuit for correcting nonlinear behavior of the power amplifier and a power amplification system employing the circuit. Additionally, the present invention relates to a method for compensating for nonlinearity of the power amplifier. This application for the power amplifier correction circuit is based on Korean patent application No. 2001-8798, which is incorporated by reference herein for all purposes.
2. Description of Related Arts
A signal transmission stage of a wireless communications system typically includes at least one high power amplifier (HPA) for providing enough power gain to a transmitted signal. Examples of the apparatus or subsystem employing such high power amplifier include satellites and control stations in a satellite communications system, mobile stations and base stations in a cellular communications network, and signal transmission units in a broadcasting system. Intrinsically, the high power amplifier shows nonlinear behavior, which distorts phase and amplitude characteristics of an input signal and introduces or increases intermodulation distortion. Considering the trend that the frequency bandwidth of communication systems is being widened and the use of multiple carriers is generalized, the intermodulation distortion is not preferable because it influences neighboring frequency bands or frequency allocations. Thus, the intermodulation distortion is restricted within a certain limit, the details of which depend on applications. Since the nonlinearity of the high power amplifier increases with the magnitude of its output power, manufacturers or service providers usually use a plurality of amplifiers in combination with a power divider and a power combiner so as to reduce the distortion even when a single power amplifier has sufficient power rating, which increases manufacturing cost or network construction cost.
One approach for reducing the nonlinearity effect of the high power amplifier is the use of a feed-forward distortion correction circuit. Such circuits are disclosed, for example, in U.S. Pat. No. 4,629,996 issued Dec. 16, 1986 to Tatsuo Watanabe et al. and entitled FEED-FORWARD MICROWAVE POWER AMPLIFIER WITH DIFFERENCE SIGNAL DISTORTION CANCELLATION CIRCUIT and U.S. Pat. No. 5,148,117 issued Sep. 15, 1992 to Ashok K. Talwar and entitled ADAPTIVE FEED-FORWARD METHOD AND APPARATUS FOR AMPLIFIER NOISE REDUCTION. According to this method, the distortion in the output signal of the amplifier is extracted and amplified to an appropriate level in a feed-forward path, and then injected to the output terminal of the amplifier through a directional coupler so as to compensate for the nonlinearity effect. The amplification of the distortion in the feed-forward path, however, requires a separate amplifier showing linear behavior and the precise calibration of analog components, which increase the system costs.
Another approach for reducing the nonlinearity effect of the high power amplifier is the predistortion of the input signal. According to this method, the input signal is predistorted in front of the power amplifier according to a modeling scheme which is the inverse of the distortion caused by the power amplifier. The inverse modeling scheme may be adaptively adjusted so that the predistortion level is changed according to the magnitude of the output signal. U.S. Pat. No. 6,118,335 issued Sep. 12, 2000 to Jorgen S. Nielson et al. and entitled METHOD AND APPARATUS FOR PROVIDING ADAPTIVE PREDISTORTION IN POWER AMPLIFIER AND BASE STATION UTILIZING THE SAME and U.S. Pat. No. 6,141,390 issued Oct. 31, 2000 to Armando Kova and entitled PREDISTORTION IN A LINEAR TRANSMITTER USING ORTHOGONAL KERNELS may be the evidences of the method.
In the conventional predistortion apparatuses, however, the predistortion of the input signal is typically carried out in baseband. Accordingly, separate signal processing circuits need to be provided for an in-phase component (I) and a quadrature component (Q) of the baseband signal, which increases the complexity of the circuit. In the case that the predistortion is performed by digital signal processing, the software algorithm or computation burden might be increased as well. Further, the complexity of the amplifying stage and resulting increase of the manufacturing cost are more severe in a wideband communications system or a system using plural carriers since the high power amplifier and the predistortion circuit is to be provided for each channel or frequency assignment.
In U.S. Pat. No. 5,877,653 issued Mar. 2, 1999 and entitled LINEAR POWER AMPLIFIER AND METHOD FOR REMOVING INTERMODULATION DISTORTION WITH PREDISTORTION SYSTEM AND FEED FORWARD SYSTEM, Kim et al. describe a system in which the intermodulation distortion is removed using both the predistortion scheme and the feed-forward scheme. Such a system, however, may complicate the system configuration further.
To solve the above problems, one object of the present invention is to provide a device for compensating for the nonlinearity of a power amplifier which has a simple configuration and can precisely linearize the transfer characteristics of the power amplifier by predistorting an input signal of the power amplifier.
Another object of the present invention is to provide a method for linearizing the transfer characteristics of an amplifier in a power amplification system to remove the distortion caused by the power amplifier.
In order to achieve one of the above objects, the nonlinearity compensation device of the present invention converts a RF input signal into an IF band rather than a baseband and predistorts the IF input signal in a digital domain. A first downconverter receives the RF input signal and converts the frequency band of the RF input signal into the IF band to output an IF input signal. A predistortion unit receives and predistorts the IF input signal to compensate for the nonlinearity and outputs an IF predistorted signal. An upconverter converts the frequency band of the IF predistorted signal into the RF band to provide a RF predistorted signal to the amplifier. A second downconverter receiving a RF output signal of the amplifier through a coupler connected to an output terminal of the amplifier and converts the frequency band of the RF output signal into the IF band to provide an IF output signal to the predistortion unit. Here, the predistortion unit determines a predistortion level based on the IF input signal and the IF output signal.
In a preferred embodiment, the predistortion unit includes a memory, a look-up table, a first and a second analog-to-digital converters, a mapping and storing unit, a digital-to-analog converter, and a mapping information generator. The look-up table stores mapping information. The first analog-to-digital converter converts the IF input signal into a first digital data. The second analog-to-digital converter converts the IF output signal into a second digital data. The mapping and storing unit receives the first and the second digital data, predistorts the first digital data using the mapping information, and outputs predistorted data corresponding to the first digital data. Also, the mapping and storing unit stores at least some of the first digital data and at least some of the second digital data. The digital-to-analog converter converts the predistorted data into the IF predistorted signal. The mapping information generator generates the mapping information using the first and the second digital data.
According to the method of compensating for nonlinearity of the amplifier for achieving another one of the above objects, (a) the frequency band of a RF input signal is downconverted into an IF band. Subsequently, (b) the downconverted IF signal is predistorted to compensate for the nonlinearity of the amplifier. Finally, (c) the predistorted IF signal is upconverted into the RF band and the upconverted signal is provided to the amplifier so that the amplifier amplifies the upconverted signal.
It is preferable that the step (b) includes the steps of: (b1) providing mapping information; (b2) converting the downconverted IF signal to digital data to generate a first digital data; (b3) determining predistorted data corresponding to the first digital data using the mapping information; and (b4) converting the predistorted data to an analog signal to generate the predistorted IF signal.
The mapping information is periodically updated in a preferred embodiment. For this purpose, an amplified signal output by the amplifier is converted into a second digital data. After a cross correlation value between the first and the second digital data is calculated, the delay between the first and the second digital data is estimated based on the cross correlation value and the delay is compensated. Afterwards, the mapping information is updated by a fixed point iteration based on a predetermined amplifier model using the first and the second digital data.
Preferably, the amplifier model is represented by a third order polynomial of a following equation:
y(n)=ax(n)+bx(n)3                                                         a              =                                                                                          ∑                                              n                        =                        0                                                                    L                        -                        1                                                              ⁢                                                                  x                        ⁡                                                  (                          n                          )                                                                    ⁢                                              y                        ⁡                                                  (                          n                          )                                                                    ⁢                                                                        ∑                                                      n                            =                            0                                                                                L                            -                            1                                                                          ⁢                                                                              x                            6                                                    ⁡                                                      (                            n                            )                                                                                                                                -                                                            ∑                                              n                        =                        0                                                                    L                        -                        1                                                              ⁢                                                                                            x                          3                                                ⁡                                                  (                          n                          )                                                                    ⁢                                              y                        ⁡                                                  (                          n                          )                                                                    ⁢                                                                        ∑                                                      n                            =                            0                                                                                L                            -                            1                                                                          ⁢                                                                              x                            4                                                    ⁡                                                      (                            n                            )                                                                                                                                              D                                                                                        b              =                                                                                          ∑                                              n                        =                        0                                                                    L                        -                        1                                                              ⁢                                                                                            x                          3                                                ⁡                                                  (                          n                          )                                                                    ⁢                                              y                        ⁡                                                  (                          n                          )                                                                    ⁢                                                                        ∑                                                      n                            =                            0                                                                                L                            -                            1                                                                          ⁢                                                                              x                            2                                                    ⁡                                                      (                            n                            )                                                                                                                                -                                                            ∑                                              n                        =                        0                                                                    L                        -                        1                                                              ⁢                                                                  x                        ⁡                                                  (                          n                          )                                                                    ⁢                                              y                        ⁡                                                  (                          n                          )                                                                    ⁢                                                                        ∑                                                      n                            =                            0                                                                                L                            -                            1                                                                          ⁢                                                                              x                            4                                                    ⁡                                                      (                            n                            )                                                                                                                                              D                                                                                      where          ⁢                      xe2x80x83                    ⁢          D                =                                            ∑                              n                =                0                                            L                -                1                                      ⁢                                                            x                  2                                ⁡                                  (                  n                  )                                            ⁢                                                ∑                                      n                    =                    0                                                        L                    -                    1                                                  ⁢                                                      x                    6                                    ⁡                                      (                    n                    )                                                                                -                                    [                                                ∑                                      n                    =                    0                                                        L                    -                    1                                                  ⁢                                                      x                    4                                    ⁡                                      (                    n                    )                                                              ]                        2                              
Here, x(n) and y(n) denotes the first and the second digital data, respectively. Also, the fixed point iteration is expressed by a following equation:
taddr(k+1)=taddr(k)+xcex1[gtaddr(0)xe2x88x92ataddr(k)xe2x88x92btaddr(k)3], 
where
addr=0, 1, 2, . . . , Nxe2x88x921 (address in the mapping information),
k=0, . . . , M (iteration number),
taddr (0) is an initial value,
g is a linear gain, and
xcex1 is a step size (positive number).
The present invention facilitates to linearize an amplified signal by predistorting the input signal of the amplifier based on the fixed point iteration without calculating an inverse function of the transfer function of the amplifier. Since the mapping information in the LUT is updated adaptively, the present invention enables to obtain the consistent amplification behavior regardless of the signal properties and the operation environment such as the temperature of the power amplifier, and allows each device employing components of different figures to have almost the same performance with one another. The present invention enables the mass production and can lowers the manufacturing cost of the device because most portion of the circuit is implemented by use of digital components. Since the nonlinearity compensation device predistorts the signal in the IF band, the present invention obviates any modulation or demodulation process and allows the simultaneous processing of signals in multiple channels.